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Articles
| High-Speed 4 BIT Flash ADC Using CMOS Latched Comparator with Current Steering Logic SR Latch |
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| A. Karthikeyan, V. Srividhya, P. Murugeswari | 168-174 |
| Large Radial Distribution Network Optimization through Algorithm Design Technique |
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| S. Thiruvenkadam, Dr. A. Nirmalkumar, M. Sathiskumar | 175-182 |
| A Novel AES VLSI Architecture with Fully-Sub Pipelined Structure for High Throughput and Area Efficiency |
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| R. Sakthivel, S. Balamurugan, M. Vanitha | 183-188 |
| Design and Development of Microstrip Patched Antenna Array |
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| P. Laksminarayana, Mahesh Mudavath, V. Omjee, K. Kumara Swamy | 189-196 |
| Network-on-Chip Design Space Exploration: A Hybrid Approach |
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| Rabindra K Jena, Dr. Pankaj Srivastav, Dr. G. K. Sharma | 197-203 |
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